We do functional verification and timing verification(STA) before we tape out, why then do we still need to do validation after silicon come back?  It should just work, correct?

Well, the reasons are:

1.  The functional verificaion is incomplete (e.g, the Debug/IDE is typically not verified; Not all scenarios were cosidered during verification)

2.  The STA is incomplete (e.g. SDC file did not constrain certain ports like JTAG, or have set incorrect false paths)

3.  (rare) The fab model(CMOS) and/or std/memory models are inaccurate!

So, we need validation to catch the "unexpected" things.

Categories:

1. Sub-system level: check if a lower-level sub-system/module/IP functions correctly

2. System-level: check if top-level behavior is correct or not, often done on the chip hardware with firmware/OS/application together

3.  Electrical: e.g. signal integrity, serial interface speed

4.  Analog: e.g. PLL, LDO, ADC/DAC

5.  PVT:  extreme timing corners

Required Skills

1. Soc/ASIC Architecture

2. Processors

3. Protocols (USB, AMBA, etc)

4. Analog

5. Programming (Shell scripts, Python/Perl)

6. Lab Equipment Knowledge

7. System-level Skills (PCB schematics, typical use-cases)

8.  Debugging Skills

Interesting Stats:

Engineering resources spent on a product: Design/Verification/Implementation/Validation=25/35/20/20